As the scale of integrated circuit designs is increasingly reduced, power supply voltages to the integrated circuits are also reduced. However, the integrated circuit designs receive signals at higher voltage levels even though the internal power available for the circuit designs may be reduced below the voltage level of certain received signals.
For example, an on-chip supply voltage of an integrated circuit design may be in a range of about 1.8 volts. Receiver circuitry on the chip may be required to handle high voltage domain I/O signals in a range of 0V to 3.6 V. The high voltage domain I/O signals would saturate amplifiers of the receiver circuitry if the high voltage domain signals were directly connected to the chip. Thus, a receiver circuit operating in the 1.8 V domain could not reliably receive a directly connected signal above a common mode of 1.8 volts. Complex circuit designs involving source followers, voltage regulators, level selection logic, etc., have been required to interface the high voltage domain I/O signals with low voltage domain receiver circuit designs.
Certain circuit designs such as those compatible with USB 2.0, have both differential receivers and single ended receivers. In these circuit designs, the differential receivers are handled separately from the single ended receivers. A large amount of area on a chip is consumed to facilitate handling of both receiver types.